CPU & ArchitectureCPU 1 How a CPU Executes Instructions
A focused technical guide to CPU 1 How a CPU Executes Instructions, covering Micro-Labs and Tracing a Simple Instruction Sequence.
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CPU & Architecture
CPU & ArchitectureCPU 19 Atomics Memory Ordering
A focused technical guide to CPU 19 Atomics Memory Ordering, covering Memory Reordering Fundamentals and Compiler vs Hardware Effects.
CPU & ArchitectureCPU 18 Branch Prediction Speculation
A focused technical guide to CPU 18 Branch Prediction Speculation, covering Introduction to Branch Prediction and Overview of Modern Prediction Strategies.
CPU & ArchitectureCPU 17 RISC V Privilege Traps and Syscalls
A focused technical guide to CPU 17 RISC V Privilege Traps and Syscalls, covering Interrupts and Synchronous vs Asynchronous Events.
CPU & ArchitectureCPU 16 RISC V RV64I
A focused technical guide to CPU 16 RISC V RV64I, covering Introduction and Function Prologues and Epilogues.
CPU & ArchitectureCPU 15 RISC V RV32I Assembly
A focused technical guide to CPU 15 RISC V RV32I Assembly, covering Memory Access Discipline and Memory as an Explicit Resource.
CPU & ArchitectureCPU 14 AArch64 Exceptions Syscalls
A focused technical guide to CPU 14 AArch64 Exceptions Syscalls, covering Overview of Privilege Levels.
CPU & ArchitectureCPU 13 AArch64 Calling Convention
A focused technical guide to CPU 13 AArch64 Calling Convention, covering CPU Programming Series AArch64 Calling Convention (AAPCS64) C/C++ Interoperability in Practice Prepared by Ayman Alheraki simplifycpp.org January 2026 Contents Content
CPU & ArchitectureCPU 12 AArch64 Core Architecture
A focused technical guide to CPU 12 AArch64 Core Architecture, covering Memory Access vs Register Operations.