CPU 2 Registers Flags and Data Representation

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• CPU Programming Series Registers, Flags, and Data Representation Binary Reality for Assembly Programmers Prepared by Ayman Alheraki simplifycpp.org November 2025 Contents Contents 2 Preface 6 Why This Booklet Exists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 What “Binary Reality” Really Means . . . . . . . . . . . . . . . . . . . . . . . . . . 6 What This Booklet Does Not Cover . . . . . . . . . . . . . . . . . . . . . . . . . . 7 How to Read This Booklet Effectively . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 Bits, Registers, and the Machine View 9 1.1 What a Register Really Is (Beyond the Name) . . . . . . . . . . . . . . . . . . 9 1.2 Bit Width, Lanes, and Hardware Limits . . . . . . . . . . . . . . . . . . . . . 9 1.3 Logical vs Physical Interpretation of Bits . . . . . . . . . . . . . . . . . . . . 10 1.4 Registers as Raw Containers (No Types, No Meaning) . . . . . . . . . . . . . 10 1.5 When Meaning Emerges: Instruction Context . . . . . . . . . . . . . . . . . . 11 2 Bits, Registers, and the Machine View 12 2.1 What a Register Really Is (Beyond the Name) . . . . . . . . . . . . . . . . . . 12 2.2 Bit Width, Lanes, and Hardware Limits . . . . . . . . . . . . . . . . . . . . . 13 2.3 Logical vs Physical Interpretation of Bits . . . . . . . . . . . . . . . . . . . . 13 2.4 Registers as Raw Containers (No Types, No Meaning) . . . . . . . . . . . . . 14 2 3 2.5 When Meaning Emerges: Instruction Context . . . . . . . . . . . . . . . . . . 15 3 Signed vs Unsigned: Same Bits, Different Truths 16 3.1 Why the CPU Does Not Know “Signed” . . . .