Intel x86 64 Instruction Set Quick Reference
A focused technical guide to Intel x86 64 Instruction Set Quick Reference, covering Intel x86-64 Instruction Set Quick Reference Prepared by Ayman Alheraki simplifycpp.org March 2025 Contents Contents 2 Author’s Note 7 1 Registers & Flags 1
About this book
Intel x86 64 Instruction Set Quick Reference is a technical book in CPU & Architecture. Its opening contents highlight Intel x86-64 Instruction Set Quick Reference Prepared by Ayman Alheraki simplifycpp.org March 2025 Contents Contents 2 Author’s Note 7 1 Registers & Flags 10 1.1 General Purpose Registers (RAX–R15) . . . . . . . . . . . . . 10 1.2 Pointer & Index Registers (RSP, RBP, RSI, RDI) . . . . . . . . 12 1.3 Instruction Pointer (RIP) . . . . . . . . . . . . . . . . . . . . . 14 1.4 Segment Registers (CS, DS, ES, FS, GS, SS) . . . . . . . . . . 15 1.5 Flags Register (RFLAGS) . . . . . . . . . . . . . . . . . . . . . 16 1.6 Vector Registers . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.7 Mask Registers (K0–K7, AVX-512) . . . . . . . . . . . . . . . 22 1.8 Control & Debug Registers (CR0–CR8, DR0–DR7) . . . . . . . 23 2 Core Integer Instructions 25 2.1 Data Movement Instruct
Inside the book
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- Intel x86-64 Instruction Set Quick Reference Prepared by Ayman Alheraki simplifycpp.org March 2025 Contents Contents 2 Author’s Note 7 1 Registers & Flags 10 1.1 General Purpose Registers (RAX–R15) . . . . . . . . . . . . . 10 1.2 Pointer & Index Registers (RSP, RBP, RSI, RDI) . . . . . . . . 12 1.3 Instruction Pointer (RIP) . . . . . . . . . . . . . . . . . . . . . 14 1.4 Segment Registers (CS, DS, ES, FS, GS, SS) . . . . . . . . . . 15 1.5 Flags Register (RFLAGS) . . . . . . . . . . . . . . . . . . . . . 16 1.6 Vector Registers . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.7 Mask Registers (K0–K7, AVX-512) . . . . . . . . . . . . . . . 22 1.8 Control & Debug Registers (CR0–CR8, DR0–DR7) . . . . . . . 23 2 Core Integer Instructions 25 2.1 Data Movement Instructions . . . . . . . . . . . . . . . . . . . 25 2 3 2.2 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . 27 2.3 Multiplication/Division Instructions . . . . . . . . . . . . . . . 28 2.4 Bitwise Instructions . . . . . . . . . . . . . . . . . . . . . . . . 29 2.5 Shift & Rotate Instructions . . . . . . . . . . . . . . . . . . . . 30 2.6 BCD / Legacy Instructions (Short Note) . . . . . . . . . . . . . 31 3 Control Flow 32 3.1 Jumps & Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 Conditional Branches (Jcc) . . . . . . . . . . . . . . . . . . . . 34 3.3 Looping Instructions . . . . . . . . . . . . . . . . . . . . . . . 35 3.4 Set on Condition (SETcc) . . . . . . . . . . . . . . . . . . . . . 36 3.5 Conditional Moves (CMOVcc) . . . . . . . . . . . . . . . . . . 37 4 Stack & Pr
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