CPU & ArchitectureCPU 3 The Stack Calling Conventions
A focused technical guide to CPU 3 The Stack Calling Conventions, covering Calling Conventions and What a Calling Convention Defines.
Processor architecture, instruction execution, memory hierarchy, x86-64, ARM, and RISC-V.
CPU & ArchitectureA focused technical guide to CPU 3 The Stack Calling Conventions, covering Calling Conventions and What a Calling Convention Defines.
CPU & ArchitectureA focused technical guide to CPU 2 Registers Flags and Data Representation, covering CPU Programming Series Registers, Flags, and Data Representation Binary Reality for Assembly Programmers Prepared by Ayman Alheraki simplifycpp.org Novembe
CPU & ArchitectureA focused technical guide to CPU 22 RISC V Vector Extension RVV, covering Compiler Interaction and Toolchain Behavior and Performance Characteristics and Pitfalls.
CPU & ArchitectureA focused technical guide to CPU 21 NEON on AArch64, covering Programming NEON and Compiler Auto-Vectorization.
CPU & ArchitectureA focused technical guide to CPU 20 SIMD on x86 SSE, covering CPU Programming Series SIMD on x86: SSE AVX Practical Patterns Prepared by Ayman Alheraki simplifycpp.org February 2026 Contents Contents 2 Preface 15 Scope and Philosophy of Thi
CPU & ArchitectureA focused technical guide to CPU 1 How a CPU Executes Instructions, covering Micro-Labs and Tracing a Simple Instruction Sequence.
CPU & ArchitectureA focused technical guide to CPU 19 Atomics Memory Ordering, covering Memory Reordering Fundamentals and Compiler vs Hardware Effects.
CPU & ArchitectureA focused technical guide to CPU 18 Branch Prediction Speculation, covering Introduction to Branch Prediction and Overview of Modern Prediction Strategies.
CPU & ArchitectureA focused technical guide to CPU 17 RISC V Privilege Traps and Syscalls, covering Interrupts and Synchronous vs Asynchronous Events.